1. Field of the Invention
This invention relates to semiconductor integrated circuits and, more particularly, to shielding structures and metallization layers within semiconductor integrated circuits.
2. Description of the Related Art
Integrated Circuits (ICs) are manufactured using complex processes including a variety of specific processing steps. Typically, the solid-state devices that make up an IC are formed on the surface (or substrate) of a semiconducting material such as silicon, for example. Although silicon has been the most widely used semiconducting material, other materials such as Gallium-Arsenide (GaAs) and Silicon-Germanium (SiGe) have also become popular for certain applications including analog and specialty integrated circuits. Once the devices have been formed, the individual components are interconnected. The devices are typically interconnected by metal lines or wires made from aluminum, copper, tungsten or some other conductive material. The metal lines are typically manufactured by depositing layers of metal over the entire surface of the wafer and then precisely etching away areas other than those defining the metal lines. Due to the high density of devices, most modern ICs include multiple metal layers that may be separated by an interlayer dielectric (ILD).
Analog circuits and especially high frequency analog circuits can be susceptible to noise. The operation of such circuits may be affected adversely when placed in noisy environments. This may be particularly true of analog and mixed signal integrated circuits. Mixed signal ICs may include both analog and digital circuits that are manufactured on the same semiconducting substrate. Noise and spurious signals generated by one circuit may adversely affect the operation of other circuitry. For example, the digital circuits can generate switching noise that may detrimentally affect the operation of analog circuits that are nearby or are otherwise coupled to the digital circuits.
In some IC designs, it may thus be desirable to shield signals from one another from a capacitive coupling point of view. This is often accomplished by introduction of metal lines and/or metal planes between the signal regions. Although this approach works adequately in some IC designs, in designs that require the shielding of numerous important signals, a very high metal density may result from the use of large amounts of metal plane shielding. Unfortunately, many fabrication technologies impose strong restraints on high metal densities to avoid dishing and other manufacturing problems.
In addition, while in many IC designs shielding of signals from an inductive point of view is generally not considered, at gigahertz frequencies and with thick metals, reasonable attenuation of magnetic fields through continuous metal planes may be attained. As stated above, however, continuous metal planes are generally not allowed (or are disfavored) in many fabrication technologies due to manufacturability issues.
It is also sometimes necessary that characteristics of different components in an IC be precisely matched. For example, it may be desirable to precisely match the electrical characteristics (e.g., capacitance values) of different capacitors formed within an IC. Depending on the type of capacitor and the specific manufacturing process, conventional trimming techniques may not be viable or desirable. Another method used to accomplish matching may include the use of a continuous metal plane shield to create a matched environment for the capacitors. However, as stated above, in addition to the manufacturability issues associated with the high metal density of continuous metal plane shields, the possibility of dishing may also hinder the ability to create a matched environment.
Finally, it is also sometimes desirable in IC designs for manufacturability reasons to ensure good planarization and consistent metal uniformity. Typically the goal is to increase the metal density to above 20% but below about 70% or 80% in a uniform way. Fill programs are commonly used to add metal dummy fill structures wherever it is considered necessary. However, in some designs such as analog designs, the dummy metal fill structures are not desirable since they may detrimentally affect performance.
It would accordingly be desirable to provide an integrated circuit structure that may provide suitable capacitive shielding, suitable inductive shielding and/or desired metal uniformity or increased metal density without the manufacturability problems associated with continuous metal planes.